1. Field of the Invention
The present invention relates to a substrate having a microstrip line structure composed of a base body that is a semiconductor or an insulator, a semiconductor device having a microstrip line structure, and a manufacturing method of a substrate having a microstrip line structure.
2. Description of Related Art
Conventionally, in the field of semiconductors, the scale down of process technique has been regarded as an important index of product development, and miniaturization, high-level function, and low electric power consumption of large scale integration (LSI) have been realized by process technology similar to a system on a chip (SOC) to integrate a variety of functions on one chip.
In a SOC, however, there are the problems of a short period of product cycle and difficulties in reducing the development cost associated therewith. For the purpose of complementing this, there has been used a technique by means of a multi chip module (MCM) for mounting a wide variety of dies/chips on a single package. Since the technique is able to appropriate directly a developed die/chip in the MCM, there are the merits of a short period of development and a reduction in development cost. In addition, the point of enabling integration of large-capacity flash memories and DRAMs, which has been difficult in a SOC and a problem in the manufacturing process, also can be said to be an advantage of the MCM.
Recently, the difficulties in complying with an increase in mounting a number of parts, which is caused by a deficiency of mounting area and the like, become significant in equipment having a semiconductor device, particularly portable equipment, and the limit of mounting by the SOC is also pointed out.
The solution to this problem shows increasingly the tendency to decrease the mounting area by, for example, a MCM of a stack type in which a plurality of chips are stacked vertically. That is, the understanding of the MCM is changing from one means for complementing a SOC to the main mounting technique in semiconductor technology.
In this MCM, a substrate constituting an interposer having a microstrip line structure is used.
On the other hand, there was proposed the formation of a microstrip line structure on the surface of a substrate composed of silicon (for example, Patent Document 1).
[Patent Document 1]
Japanese Patent Application Publication No. 7-336114 (FIG. 1, paragraph No. “0006”).
Meanwhile, in the case of applying voltage to two adjacent conductors, if the voltage is direct current, or even if it is alternating current, but the frequency is low, only the influence due to the resistances possessed by the two conductors is exerted on the mutual conductors and their internal currents. In contrast, if the frequency enters the microwave band in alternating current, the mutual influence occurs even by the electric field caused by the inductance of the conductors themselves and the capacitance between the conductors.
The influence of this problem is further increased by the nature of the microwave, resulting from its frequency height, which flows intensively in the vicinity of the surface of a conductor rather than the inside, which is generally called “skin effect.”
Hence, in a substrate having a microstrip line structure, the mutual influence in each wiring is liable to occur than in a general substrate, and as a result, it might interfere even with the overall operation of a semiconductor device having this substrate.
Therefore, in general, when manufacturing a MCM, also in view of the tendency to elongate the wiring of a SOC, if a substrate is one having difficulties in adding an allowance for the distance between respective wiring, such as an interposer, it is desirable to reduce the mutual influence between the respective wiring as much as possible.
In addition, although attempts also have been made to form a wiring part of a microstrip line structure by cutting trenches in a substrate, of which a cross section is a rectangle, the microstrip line structure with this construction suffers from problems due to poor coverage in the interlayer adhesion, such as between an insulating layer and a conductive layer, as well as defects in respective layers and the occurrence of leaks due to the defects.